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by George J. Milne
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George J. Milne, Laurence Pierre. Formal verification is emerging as a plausible alternative to exhaustive simulation for establishing correct digital hardware designs.
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Publications citing this paper. Showing 1-2 of 2 citations. Verifying Parameterized Recursive Circuits Using Transformations of Nets Verifying Parameterized Recursive Circuits Using Transformations of Nets. Deriving Bit-Serial Circuits in Ruby. Geraint Jones, Mary Sheeran.
Verification of VLSI circuits using L. roceedings of the IFIP WG 1. Conference on the Fusion of Hardware Design . Retiming and slowdown in Ruby
Verification of VLSI circuits using L. Conference on the Fusion of Hardware Design and Verification. Amsterdam, North Holland, 1988, pp. 329–345. 3. John Rushby and Friedrich von Henke. Formal verification of the interactive convergence clock synchronization algorithm usingehdm. SRI International report SRI-CSL-89-3, February, 1989. Retiming and slowdown in Ruby. InThe Fusion of Hardware Design and Verification, George J. Milne, (e. Amsterdam, North-Holland, 1988, pp. 289–308.
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Milne, GJ 1984, MODEL FOR HARDWARE DESCRIPTION AND VERIFICATION. Milne, George J. Proceedings - Design Automation Conference. Wiley-IEEE Press, 1984. in Proceedings - Design Automation Conference. Wiley-IEEE Press, pp. 251-257. Model for hardware description and verification. Ty - gen. T1 - model for hardware description and verification. AU - Milne, George J. Py - 1984/1/1.
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